Circuit board and method for manufacturing the same

ABSTRACT

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

RELATED APPLICATIONS

This application claims priority to China Application Serial Number201610852933.2, filed Sep. 27, 2016, which are herein incorporated byreference.

BACKGROUND Technical Field

The present disclosure relates to a circuit board and a method formanufacturing the same.

Description of Related Art

With the rapid growth of the electronics industry, the R & D ofelectronic products has gradually been directed to the pursuit ofversatility and high performance. In order to achieve the requirementsof high integration and miniaturization of semiconductor components, therequirements of circuit boards also increase. For example, the pitch ofthe traces of the circuit board is required to become smaller andsmaller, and the thickness of the circuit board is required to becomesmaller and smaller.

To further improve the circuit boards, persons in the industry have madeevery endeavor to discover new solutions. The application andimprovement of the circuit boards has become one of the most importantresearch topics.

SUMMARY

This disclosure provides a circuit board and a method for manufacturingthe same to increase the space for the circuit layer in the circuitboard and increase the overall process yield.

In one aspect of the disclosure, a method for manufacturing a circuitboard is provided. The method includes: forming a first sacrificialmetal layer on a carrier, in which the first sacrificial metal layer hasa plurality of first openings; forming a first etching stop layer on thecarrier, in which the first etching stop layer covers the firstsacrificial metal layer; forming a patterned resist on the first etchingstop layer, in which the patterned resist has a plurality of secondopenings and a intaglioed pattern, the second openings respectivelycorrespond to the first openings to expose a part of the firstsacrificial metal layer, and the intaglioed pattern exposes a part ofthe first etching stop layer; forming a plurality of metal bump in thefirst openings and the second openings and forming a first circuit layerin the intaglioed pattern; removing the patterned resist; forming abuild-up structure on the first etching stop layer, in which thebuild-up structure includes a dielectric layer, a plurality ofconductive vias, and at least one second circuit layer, the dielectriclayer covers the metal bumps and the first circuit layer, the conductivevias is formed in the dielectric layer, the second circuit layer isformed on the dielectric layer, the conductive vias connects the firstcircuit layer and the second circuit layer; a second etching stop layeris formed on the dielectric layer, in which the second etching stoplayer covers the second circuit layer; separating the carrier and thefirst sacrificial metal layer; performing a first etching process toremove the first sacrificial metal layer; and performing a secondetching process to remove the first etching stop layer and the secondetching stop layer.

In one or more embodiments, the first etching stop layer and the secondetching stop layer are made of the same material, and the first etchingstop layer and the second etching stop layer are made of tin, titanium,aluminum, or any combination thereof.

In one or more embodiments, the method further includes forming a metallayer on the dielectric layer when the build-up structure is formed. Thesecond etching stop layer further covers the metal layer. The methodfurther includes performing a third etching process to pattern the metallayer after the second etching process is performed.

In one or more embodiments, the method further includes: forming asecond sacrificial metal layer on the second etching stop layer; andremoving the second sacrificial metal layer when the first sacrificialmetal layer is removed.

In one or more embodiments, a thickness of the first sacrificial metallayer is substantially the same with a thickness of the secondsacrificial metal layer, and the first sacrificial metal layer and thesecond sacrificial metal layer are made of the same material.

In one or more embodiments, each of the metal bumps are further dividedinto a first part and a second part. After the first etching stop layerand the second etching stop layer are removed, the first part isdisposed in the dielectric layer, the second part protrudes from thedielectric layer, and a difference between widths of the first part andthe second part is less than 4% of the width of the second part.

In one or more embodiments, one of a plurality of the second circuitlayers is formed on the dielectric layer, the others of the secondcircuit layers are formed in the dielectric layer, a part of theconductive vias connect the first circuit layer and the lowermost one ofthe second circuit layers, and the others of the conductive vias connectthe second circuit layers.

In another aspect of the disclosure, a circuit board is provided. Thecircuit board includes a first dielectric layer, a first circuit layer,a second circuit layer, a conductive via, and a metal bump. The firstdielectric layer has a first surface and a second surface opposite tothe first surface. The first circuit layer is buried in the firstsurface. The second circuit layer is disposed on the second surface. Theconductive via is disposed in the first dielectric layer and connectsthe first circuit layer and the second circuit layer. The metal bump hasa first part and a second part, in which the first part is disposed inthe first dielectric layer, the second part protrudes from the firstsurface, and a difference between widths of the first part and thesecond part is less than 4% of the width of the second part.

In one or more embodiments, the circuit board further includes a seconddielectric layer disposed on a sidewall of the second part.

In one or more embodiments, an end surface of the first part and aninterface between the first circuit layer and the conductive via arecoplanar.

In one or more embodiments, an end surface of the first circuit layerexposed by the first surface and the first surface are coplanar.

In one or more embodiments, an edge of the first part is located outsidea scope enclosed by an edge of the second part.

In one or more embodiments, an edge of the first part is located in ascope enclosed by an edge of the second part.

In the aforementioned embodiments, the size of the metal bumps areeffectively controlled, such that the shape of the cross-section of eachof the metal bumps is similar to “I”, in which the widths of differentsegments of each of the metal bumps are substantially the same.Therefore, the metal bumps will not occupy the surrounding space, so thespace for the circuit layer can be effectively increased.

Further, because the first etching stop layer and the second etchingstop layer are made of tin, titanium, aluminum, or other metals that canform an intermetallic compound with copper, the first etching stop layerand the second etching stop layer will not be influenced by the alkalineetching process (the first etching process). Compared to theconventional material nickel, tin, titanium, aluminum, or other metalsthat can form an intermetallic compound with copper can resist thealkaline etching more effectively, so the cavity will not be formedafter the alkaline etching process is performed, such that depressionsor cavities may not generated in the metal bumps, the first circuitlayer, and the second circuit layer, and an open circuit will nothappen.

It is to be understood that both the foregoing general description andthe following detailed description are by examples, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the followingdetailed description of the embodiment, with reference made to theaccompanying drawings as follows:

FIGS. 1A to 1F are schematic cross-sectional views of intermediateoperations in a method for manufacturing a circuit board according toone embodiment of this disclosure;

FIG. 1C′ is a schematic cross-sectional view of one of the intermediateoperations in the method for manufacturing the circuit board accordingto another embodiment of this disclosure;

FIGS. 2A and 2B are schematic enlarged cross-sectional views of metalbumps according to one embodiment of this disclosure; and

FIGS. 3A to 3E are schematic cross-sectional views of the intermediateoperations in the method for manufacturing the circuit board accordingto another embodiment of this disclosure.

DETAILED DESCRIPTION

In the following detailed description, for purposes of explanation,numerous specific details are set forth in order to provide a thoroughunderstanding of the disclosed embodiments. It will be apparent,however, that one or more embodiments may be practiced without thesespecific details. In other instances, well-known structures and devicesare schematically depicted in order to simplify the drawings.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIGS. 1A to 1F are schematic cross-sectional views of intermediateoperations in a method for manufacturing a circuit board according toone embodiment of this disclosure. First, as shown in FIG. 1A, asacrificial metal layer 110 is formed on a carrier 100. In thisembodiment, copper foil layers 102 and 104 may be formed on the carrier100, and a stripping layer disposed between the copper foil layers 102and 104 (not shown in Figs.) may be formed. Embodiments of thisdisclosure are not limited thereto. In other embodiments, the copperfoil layers 102 and 104 may not be formed on the carrier 100. Thethickness of the copper foil layer 102 is, for example, in a range fromabout 5 μm to about 40 μm, and the thickness of the copper foil layer104 is, for example, in a range from about 1 μm to about 10 μm. Thecopper foil layers 102 and 104 may help the separating of the carrier100 and a circuit board, which is the end product, in the followingprocesses. The sacrificial metal layer 110 has a plurality of openings112. In the following processes, metal bumps will be formed in theopenings 112. The sacrificial metal layer 110 is made of metal, such ascopper. Embodiments of this disclosure are not limited thereto. Theformation method of the sacrificial metal layer 110 is, for example, anelectroplating process. In this embodiment, the openings 112 expose apart of the carrier 100.

Then, an etching stop layer 108 is formed on the carrier 100. Theetching stop layer 108 covers the sacrificial metal layer 110 and thepart of the carrier 100 exposed by the openings 112. The etching stoplayer 108 is made of tin, titanium, aluminum, or other metals that canform an intermetallic compound with copper. The formation method of theetching stop layer 108 is, for example, an electroplating process. Inthis embodiment, the etching rate of the etching stop layer 108 needs tobe smaller than the etching rate of the sacrificial metal layer 110.Therefore, in the following operation of removing the sacrificial metallayer 110 by an etching process, the etching stop layer 108 can protectthe metal bumps and the circuit layer covered by the etching stop layer108.

When the etching stop layer 108 is made of tin, copper ions in thesacrificial metal layer 110 are easy to diffuse into the etching stoplayer 108, such that the copper-tin intermetallic compound is formed.When the etching stop layer 108 is made of titanium, the copper-titaniumintermetallic compound is not easy to be formed.

When the etching stop layer 108 is made of tin, the operation of formingthe etching stop layer 108 includes the following detailed operations.First, a tin layer is formed on the carrier 100, in which the tin layercovers the sacrificial metal layer 110 and the carrier 100 exposed bythe openings 112. Then, the tin layer is heated. After the tin layer isheated, the tin layer will chemically react with the sacrificial metallayer 110, which is made of copper, and the copper foil layer 104, suchthat the tin layer becomes the etching stop layer 108 made of thecopper-tin intermetallic compound.

Then, as shown in FIG. 1B, a patterned resist 120 is formed on theetching stop layer 108. The patterned resist 120 is, for example, a dryfilm or a liquid photoresist. The patterned resist 120 has a pluralityof openings 122 corresponding to the openings 112 to expose a part ofthe etching stop layer 108. Due to the process tolerance in the processof forming the patterned resist 120, the width of the openings 122 andthe width of the openings 112 are slightly different. For example, theedge of each of the openings 122 may slightly protrude from the edge ofthe corresponding one of the openings 112 below (i.e., the width of theopenings 122 is slightly greater than the width of the openings 112, andthe edge of each of the openings 122 is located outside a scope enclosedby the edge of the corresponding one of the openings 112);alternatively, the edge of each of the openings 122 may slightly depressfrom the edge of the corresponding one of the openings 112 below (i.e.,the width of the openings 122 is slightly less than the width of theopenings 112, and the edge of each of the openings 122 is located in ascope enclosed by the edge of the corresponding one of the openings112). However, no matter the width of the opening 122 is greater or lessthan the width of the openings 112, the difference between the widths ofthe openings 112 and 122 is less than 4% of the width of the openings112.

In addition, because the difference between the widths of the openings112 and 122 is less than 4% of the width of the openings 112, the edgeof each of the openings 122 can be regarded to be aligned with the edgeof the corresponding one of the openings 112 (as shown in FIG. 1B, theedge of each of the openings 122 is aligned with the edge of thecorresponding one of the etching stop layer 108. Because the thicknessof the etching stop layer 108 is small, the edge of each of the openings122 can be regarded to be aligned with the edge of corresponding one ofthe openings 112). Furthermore, the patterned resist 120 further has aintaglioed pattern 124 exposing a part of the etching stop layer 108.

Then, a metal layer is formed in the openings 112 and 122 and theintaglioed pattern 124, such that a plurality of metal bump 130 areformed in the openings 112 and 122, and a circuit layer 140 is formed inthe intaglioed pattern 124. The metal layer is, for example, a copperlayer. The forming method of the metal layer is, for example, anelectroplating process. Each of the metal bumps 130 has a first part 130a and a second part 130 b, in which the first parts 130 a are formed inthe openings 122, and the second parts 130 b are formed in the openings112.

FIGS. 2A and 2B are schematic enlarged cross-sectional views of metalbumps according to one embodiment of this disclosure. As shown in FIG.2A, when the edge of each of the openings 122 slightly protrude from theedge of the corresponding one of the openings 112, the width of thefirst part 130 a is slightly greater than the width of the second part130 b, and the edge of the first part 130 a is located outside a scopeenclosed by the edge of the second part 130 b. The difference betweenthe widths of the openings 112 and 122 is less than 4% of the width ofthe openings 112, so the total length of the differences W1 and W2between the widths of the first part 130 a and the second part 130 b isless than 4% of the width W of the second part 130 b. As shown in FIG.1B, the shape of the cross-section of each of the metal bumps 130 issimilar to “I”, in which the widths of different segments of each of themetal bumps 130 are substantially the same.

As shown in FIG. 2B, when the edge of each of the openings 122 slightlydepress from the edge of the corresponding one of the openings 112, thewidth of the first part 130 a is slightly less than the width of thesecond part 130 b, and the edge of the first part 130 a is located in ascope enclosed by the edge of the second part 130 b. The differencebetween the widths of the openings 112 and 122 is less than 4% of thewidth of the openings 112, so the total length of the differences W1 andW2 between the widths of the first part 130 a and the second part 130 bis less than 4% of the width W of the second part 130 b. As shown inFIG. 1B, the shape of the cross-section of each of the metal bumps 130is similar to “I”, in which the widths of different segments of each ofthe metal bumps 130 are substantially the same.

Then, as shown in FIG. 1B and FIG. 10, after the patterned resist 120 isremoved, a dielectric layer 150 is formed on the etching stop layer 108.The dielectric layer 150 covers the etching stop layer 108, the firstparts 130 a, and the circuit layer 140. The dielectric layer 150 is, forexample, a prepreg. In this embodiments, the dielectric layer 150 isformed on the etching stop layer 108 by lamination. In addition, in thisembodiment, a metal layer 152 may be formed on the dielectric layer 150.The metal layer 152 is, for example, a copper layer. Embodiments of thisdisclosure are not limited thereto. In other embodiments, the metallayer 152 may not be formed on the dielectric layer 150.

Then, a plurality of via holes 154 are formed in the dielectric layer150 and the metal layer 152 to expose a part of the circuit layer 140.The forming method of the via holes 154 is, for example, laser ablation.Then, a patterned resist 160 is formed on the dielectric layer 150 andthe metal layer 152. The patterned resist 160 has a pattern 164 toexpose the via holes 154 and a part of the metal layer 152. Then, ametal layer is formed in the via holes 154 and the intaglioed pattern164, such that a plurality of conductive vias 170 are formed in the viaholes 154, and a patterned metal layer 180 is formed in the intaglioedpattern 164, in which the conductive vias 170 connect the circuit layer140 and the patterned metal layer 180. The metal layer is, for example,a copper layer. The forming method of the metal layer is, for example,an electroplating process. Therefore, the dielectric layer 150, theconductive vias 170, and the patterned metal layer 180 form a build-upstructure.

FIG. 10′ is a schematic cross-sectional view of one of the intermediateoperations in the method for manufacturing the circuit board accordingto another embodiment of this disclosure. As shown in FIG. 10′, inanother embodiment, after the patterned resist 160 and the metal layer152 covered by the patterned resist 160 are removed to form thepatterned metal layer 152 c, a dielectric layer 150′ is formed on thedielectric layer 150. The dielectric layer 150′ covers the dielectriclayer 150 and the patterned metal layer 180. The dielectric layer 150′is, for example, a prepreg. The dielectric layer 150 is formed on thedielectric layer 150 by lamination. A metal layer 152′ may be formed onthe dielectric layer 150′. The metal layer 152′ is, for example, acopper layer. In addition, the patterned metal layer 180 and the metallayer 152 c form a circuit layer 181′. Embodiments of this disclosureare not limited thereto. In other embodiments, the metal layer 152 maynot be formed, and thus the metal layer 152 c may not be formed.Therefore, the circuit layer 181′ only includes the patterned metallayer 180.

Then, a plurality of via holes 154′ are formed in the dielectric layer150 and the metal layer 152′ to expose a part of the circuit layer 181′.The forming method of the via holes 154′ is, for example, laserablation. A plurality of conductive vias 170′ are formed in the viaholes 154′, and a patterned metal layer 180′ is formed on the dielectriclayer 150′ and the metal layer 152′, in which the conductive vias 170′connect the circuit layer 181′ and the patterned metal layer 180′. Theforming methods of the conductive vias 170′ and the patterned metallayer 180′ are the same with the forming methods of the conductive vias170 and the patterned metal layer 180, so the details will not repeathere. Therefore, the dielectric layers 150 and 150′, the conductive vias170 and 170′, the patterned metal layer 180′, and the circuit layer 181′form a build-up structure. In addition, the dielectric layers 150 and150′ can be viewed as one dielectric layer in the structure perspective.

Therefore, as shown in FIG. 1C′, the patterned metal layer 180′ isformed on the dielectric layer 150′. The circuit layer 181′ is formedbetween the dielectric layers 150 and 150′. The conductive vias 170connect the circuit layer 140 and the circuit layer 181′ (the lowermostone of the patterned metal layer 180′ and the circuit layer 181′). Theconductive vias 170′ connect the circuit layer 181′ and the patternedmetal layer 180′.

The following processes in this embodiment is similar to the followingprocess in the embodiment of FIG. 1C, so the following processes in theembodiment of FIG. 1C are mainly discussed below.

As shown in FIG. 1C and FIG. 1D, the patterned resist 160 is removed.Then, an etching stop layer 188 is formed on the dielectric layer 150and the metal layer 152. The etching stop layer 188 covers the patternedmetal layer 180 and a part of the metal layer 152. The etching stoplayers 188 and 108 are made of the same material, i.e., tin, titanium,aluminum, or other metals that can form an intermetallic compound withcopper. The formation method of the etching stop layer 188 is, forexample, an electroplating process.

When the etching stop layer 188 is made of tin, the operation of formingthe etching stop layer 188 includes the following detailed operations.First, a tin layer is formed on the dielectric layer 150, in which thetin layer covers the patterned metal layer 180 and a part of the metallayer 152. Then, the tin layer is heated. After the tin layer is heated,the tin layer will chemically react with the patterned metal layer 180and the metal layer 152, which are made of copper, such that the tinlayer becomes the etching stop layer 188 made of the copper-tinintermetallic compound.

After the patterned resist 160 is removed, the metal layer 152 isusually patterned (in FIG. 1C′, the metal layer 152 is patterned to formthe metal layer 152 c). However, in this embodiment, since the tin layerwill chemically react with the metal layer 152 to form the etching stoplayer 188 made of the copper-tin intermetallic compound, the metal layer152 will not be patterned after the patterned resist 160 is removed, andthe metal layer 152 will be patterned in the following processes. Whenthe etching stop layer 108 is made of titanium or aluminum, the metallayer 152 can be patterned after the patterned resist 160 is removed.Therefore, the etching stop layer 188 will be formed on the dielectriclayer 150 and the patterned metal layer 180.

Then, a sacrificial metal layer 190 is formed on the etching stop layer188. The sacrificial metal layer 190 is, for example, a copper layer.Embodiments of this disclosure are not limited thereto. The formingmethod of the sacrificial metal layer 190 is, for example, anelectroplating process. Further, the thickness of the sacrificial metallayer 110 is substantially the same with the thickness of thesacrificial metal layer 190. In some embodiments, the thickness of thesacrificial metal layers 110 and 190 is in a range from about 10 μm toabout 30 μm. In addition, the sacrificial metal layers 110 and 190 aremade of the same material.

Then, as shown in FIG. 1D and FIG. 1E, the carrier 100 and thesacrificial metal layer 110 are separated. In this embodiment, becausethe copper foil layers 102 and 104 are disposed on the carrier 100, thecopper foil layer 102 can be easily stripped from the copper foil 104 bythe stripping layer (not shown in Figs.) to separate the carrier 100 andthe sacrificial metal layer 110 during the process of separating thecarrier 100 and the sacrificial metal layer 110.

Then, as shown in FIG. 1F, a first etching process is performed toremove the sacrificial metal layers 110 and 190. In this embodiment, thecopper foil layer 104 located below the sacrificial metal layer 110 isremoved to expose the etching stop layer 108 when the sacrificial metallayers 110 and 190 are removed.

The first etching process is an alkaline etching process. Because theetching stop layers 108 and 118 are made of tin, titanium, aluminum, orother metals that can form an intermetallic compound with copper, theetching stop layers will not be influenced by the first etching process.Compared to the conventional material nickel, tin, titanium, aluminum,or other metals that can form an intermetallic compound with copper canresist the alkaline etching more effectively, so the cavity will not beformed in the etching stop layers 108 and 118 after the first etchingprocess is performed, such that depressions or cavities may not begenerated in the metal bumps 130, the circuit layer 140, and thepatterned metal layer 180, and an open circuit will not happen.

Further, because the thickness of the sacrificial metal layer 110 issubstantially the same with the thickness of the sacrificial metal layer190, and the sacrificial metal layers 110 and 190 are made of the samematerial, the time needed to remove the sacrificial metal layer 110 andthe time needed to remove the sacrificial metal layer 190 areapproximately the same. Therefore, each of the sacrificial metal layers110 and 190 will not be removed ahead of the other, such that the timethat each of the etching stop layers 108 and 188 is influenced by thefirst etching process will not be longer than the time that the other ofthe etching stop layers 108 and 188 is influenced by the first etchingprocess, and thus defects will not be generated in each of the etchingstop layers 108 and 188.

Then, a second etching process is performed to remove the etching stoplayers 108 and 188. In the second etching process, the etchant onlyetches the etching stop layers 108 and 188 without damaging the circuitlayer 140, the patterned metal layer 180, and the metal bumps 130. Inthis embodiment, after the sacrificial stop layers 108 and 188 areremoved, a third etching process is performed to remove a part of themetal layer 152 to form a patterned metal layer 152 a, and the patternedmetal layer 180 and the metal layer 152 a form a circuit layer 181.Therefore, a circuit board 10 is formed.

As shown in FIG. 1F, in another aspect of the disclosure, the circuitboard 10 includes a dielectric layer 150, circuit layers 140 and 181, aplurality of conductive vias 170, and a plurality of metal bumps 130.The dielectric layer 150 has a surface 154 a and a surface 154 bopposite to the surface 154 a. The circuit layer 140 is buried in thesurface 154 a, and the end surface of the circuit layer 140 exposed bythe surface 154 a may be optionally coplanar with the surface 154 a.Embodiments of this disclosure are not limited thereto. In addition, thecircuit layer 181 is disposed on the surface 154 b. The conductive vias170 are disposed in the dielectric layer 150 and connect the circuitlayers 140 and 181.

As shown in FIG. 1F, each of the metal bumps 130 has a first part 130 aand a second part 130 b. The first part 130 a is disposed in thedielectric layer 150, and the second part 130 b protrudes from thesurface 154 a. In addition, the end surface of the first part 130 may beoptionally coplanar with an interface between the circuit layer 140 andone of the conductive vias 170. Embodiments of this disclosure are notlimited thereto. The shape of the cross-section of each of the metalbumps 130 is similar to “I”, in which the widths of different segmentsof each of the metal bumps 130 are substantially the same. Therefore,the metal bumps 130 will not occupy the surrounding space, so the spacefor the circuit layer can be effectively increased.

FIGS. 3A to 3E are schematic cross-sectional views of the intermediateoperations in the method for manufacturing the circuit board accordingto another embodiment of this disclosure. The embodiment in FIG. 3A toFIG. 3E is similar to the embodiment in FIG. 1A to FIG. 1F. Therefore,the differences are mainly discussed below. The description of theomitted parts can be referred to the aforementioned embodiments, and theomitted parts will not repeat below. In addition, the same element orsimilar elements will use the same reference numerals.

As shown in FIG. 3A, after the operation described in FIG. 1A, apatterned resist 220 is formed on the etching stop layer 108. Thepatterned resist 220 has a intaglioed pattern 124 to expose a part ofthe etching stop layer 108 as well. However, the difference between thepatterned resists 120 and 220 is that the patterned resist 220 coversthe sidewalls of the openings 112 to form a plurality of openings 222.Therefore, the width of the openings 222 is less than the width of theopenings 112.

Then, a metal layer is formed in the openings 222 and the intaglioedpattern 124, such that a plurality of metal bumps 230 are formed in theopenings 222 and a circuit layer 140 is formed in the intaglioed pattern124. The metal layer is, for example, a copper layer. The forming methodof the metal layer is, for example, an electroplating process. Each ofthe metal bumps 230 has a first part 230 a and a second part 230 b. Thedeposition height of the first part 230 a is substantially the same withthe deposition height of the circuit layer 140, and the second part 230b is disposed in the openings 112. Because the patterned resist 220covers the sidewalls of the openings 112 to form the openings 222, thewidths of the first part 230 a and the second part 230 b are the same.In other words, the shape of the cross-section of each of the metalbumps 230 is similar to “I”.

In addition, because the width of the openings 222 is less than thewidth of the openings 112, the width of the metal bumps 230 is less thanthe width of the metal bumps 130 in the aforementioned embodiment.Embodiments of this disclosure are not limited thereto. The width of theopenings 112 and the thickness of the patterned resist 220 covering thesidewalls of the openings 112 may be adjusted according to actualrequirements to adjust the width of the openings 222, such that thewidth of the metal bumps 230 formed in the openings 222 can further beadjusted.

Then, as shown in FIG. 3A and FIG. 3B, after the patterned resist 220 isremoved, a dielectric layer 150 is formed on the etching stop layer 108.The dielectric layer 150 covers a part of the etching stop layer 108,the first parts 230 a, and the circuit layer 140, and a part of thedielectric layer 150 (the dielectric layer 150 a) is filled in theopenings 112 and located in gaps between the second parts 230 b and theopenings 112. In other words, the dielectric layer 150 a is disposed onthe sidewalls of the second parts 230 b and covers a part of the etchingstop layer 108. By adjusting the thickness of the patterned resist 220covering the sidewalls of the openings 112, the thickness of thedielectric layer 150 a may be adjusted. Therefore, the thickness of thedielectric layer 150 a may be optionally reduced to minimum according toactual requirements, such that the dielectric layer 150 a will notinfluence the performance of the circuit board formed in the followingprocesses. The dielectric layer 150 is, for example, a prepreg. In thisembodiments, the dielectric layer 150 is formed on the etching stoplayer 108 by lamination. In addition, similar to the aforementionedembodiment, a metal layer 152 may be formed on the dielectric layer 150.

Then, a plurality of conductive vias 170 are formed in the dielectriclayer 150, and a patterned metal layer 180 is formed on the dielectriclayer 150, in which the conductive vias 170 connect the circuit layer140 and the patterned metal layer 180. The associated processes offorming the conductive vias 170 and the patterned metal layer 180 aredescribed in the aforementioned embodiment, so the detail will notrepeat here. Therefore, the dielectric layer 150, the conductive vias170, and the patterned metal layer 180 form a build-up structure.

Then, as shown in FIG. 3B and FIG. 3C, similar to the operationsdescribed in FIG. 1D, the patterned resist 160 is removed. Then, anetching stop layer 188 is formed on the dielectric layer 150 and themetal layer 152. The etching stop layer 188 covers the patterned metallayer 180 and a part of the metal layer 152.

Then, a sacrificial metal layer 190 is formed on the etching stop layer188. The associated processes of forming the sacrificial metal layer 190are described in the aforementioned embodiment, so the detail will notrepeat here.

Then, as shown in FIG. 3C and FIG. 3D, similar to the operationsdescribed in FIG. 1E, the carrier 100 and the sacrificial metal layer110 are separated.

Then, as shown in FIG. 3D and FIG. 3E, similar to the operationsdescribed in FIG. 1F, the sacrificial metal layer 110 and 190 areremoved. Similar to the aforementioned embodiment, the sacrificial metallayers 110 and 190 are removed, and the copper foil layer 104 disposedbelow the sacrificial metal layer 110 is removed as well to expose theetching stop layer 108. Then, a second etching process is performed toremove the etching stop layers 108 and 188. In this embodiment, afterthe sacrificial stop layers 108 and 188 are removed, a third etchingprocess is performed to form a patterned metal layer 152 a, and thepatterned metal layer 180 and the metal layer 152 a form a circuit layer181. Therefore, a circuit board 20 is formed.

As shown in FIG. 3E, in another aspect of the disclosure, similar to thecircuit board 10 of FIG. 1F, the circuit board 20 includes a dielectriclayer 150, circuit layers 140 and 181, a plurality of conductive vias170, and a plurality of metal bumps 230. The width of the first parts230 a of the metal bumps 230 is the same with the width of the secondpart 230 b of the metal bumps 230 b, and the shape of the cross-sectionof each of the metal bumps 130 is similar to “I”. However, thedifference between the circuit boards 10 and 20 is that the width of themetal bumps 230 of the circuit board 20 is less than the width of themetal bumps 130 of the circuit board 10. Therefore, the space for thecircuit layer can be effectively increased, and the circuit board 20 maybe further miniaturized. In addition, the circuit board 20 furtherincludes the dielectric layer 150 a, and the dielectric layer 150 a isdisposed on the sidewalls of the second parts 230 b.

All the features disclosed in this specification (including anyaccompanying claims, abstract, and drawings) may be replaced byalternative features serving the same, equivalent or similar purpose,unless expressly stated otherwise. Thus, unless expressly statedotherwise, each feature disclosed is one example only of a genericseries of equivalent or similar features.

Any element in a claim that does not explicitly state “means for”performing a specified function, or “step for” performing a specificfunction, is not to be interpreted as a “means” or “step” clause asspecified in 35 U.S.C. § 112, 6th paragraph. In particular, the use of“step of” in the claims herein is not intended to invoke the provisionsof 35 U.S.C. § 112, 6th paragraph.

What is claimed is:
 1. A method for manufacturing a circuit board,comprising: forming a first sacrificial metal layer on a carrier,wherein the first sacrificial metal layer has a plurality of firstopenings; forming a first etching stop layer on the carrier, wherein thefirst etching stop layer covers the first sacrificial metal layer;forming a patterned resist on the first etching stop layer, wherein thepatterned resist has a plurality of second openings and a intaglioedpattern, the second openings respectively correspond to the firstopenings to expose a part of the first sacrificial metal layer, and theintaglioed pattern exposes a part of the first etching stop layer;forming a plurality of metal bump in the first openings and the secondopenings and forming a first circuit layer in the intaglioed pattern;removing the patterned resist; forming a build-up structure on the firstetching stop layer, wherein the build-up structure includes a dielectriclayer, a plurality of conductive vias, and at least one second circuitlayer, the dielectric layer covers the metal bumps and the first circuitlayer, the conductive vias is formed in the dielectric layer, the secondcircuit layer is formed on the dielectric layer, the conductive viasconnects the first circuit layer and the second circuit layer; a secondetching stop layer is formed on the dielectric layer, wherein the secondetching stop layer covers the second circuit layer; separating thecarrier and the first sacrificial metal layer; performing a firstetching process to remove the first sacrificial metal layer; andperforming a second etching process to remove the first etching stoplayer and the second etching stop layer.
 2. The method of claim 1,wherein the first etching stop layer and the second etching stop layerare made of the same material, and the first etching stop layer and thesecond etching stop layer are made of tin, titanium, aluminum, or anycombination thereof.
 3. The method of claim 1, further comprising:forming a metal layer on the dielectric layer when the build-upstructure is formed; wherein the second etching stop layer furthercovers the metal layer; and performing a third etching process topattern the metal layer after the second etching process is performed.4. The method of claim 1, further comprising: forming a secondsacrificial metal layer on the second etching stop layer; and removingthe second sacrificial metal layer when the first sacrificial metallayer is removed.
 5. The method of claim 4, wherein a thickness of thefirst sacrificial metal layer is substantially the same with a thicknessof the second sacrificial metal layer, and the first sacrificial metallayer and the second sacrificial metal layer are made of the samematerial.
 6. The method of claim 1, wherein each of the metal bumps arefurther divided into a first part and a second part, after the firstetching stop layer and the second etching stop layer are removed, thefirst part is disposed in the dielectric layer, the second partprotrudes from the dielectric layer, and a difference between widths ofthe first part and the second part is less than 4% of the width of thesecond part.
 7. The method of claim 1, wherein one of a plurality of thesecond circuit layers is formed on the dielectric layer, the others ofthe second circuit layers are formed in the dielectric layer, a part ofthe conductive vias connect the first circuit layer and the lowermostone of the second circuit layers, and the others of the conductive viasconnect the second circuit layers.
 8. A circuit board, comprising: afirst dielectric layer having a first surface and a second surfaceopposite to the first surface; a first circuit layer buried in the firstsurface; a second circuit layer disposed on the second surface; aconductive via disposed in the first dielectric layer and connecting thefirst circuit layer and the second circuit layer; and a metal bumphaving a first part and a second part, wherein the first part isdisposed in the first dielectric layer, the second part protrudes fromthe first surface, and a difference between widths of the first part andthe second part is less than 4% of the width of the second part.
 9. Thecircuit board of claim 8, further comprsing: a second dielectric layerdisposed on a sidewall of the second part.
 10. The circuit board ofclaim 8, wherein an end surface of the first part and an interfacebetween the first circuit layer and the conductive via are coplanar. 11.The circuit board of claim 8, wherein an end surface of the firstcircuit layer exposed by the first surface and the first surface arecoplanar.
 12. The circuit board of claim 8, wherein an edge of the firstpart is located outside a scope enclosed by an edge of the second part.13. The circuit board of claim 8, wherein an edge of the first part islocated in a scope enclosed by an edge of the second part.